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BSI
FEATURES
Very Low Power/Voltage CMOS SRAM 128K X 16 bit
* Easy expansion with CE and OE options
BS616LV2019
* Vcc operation voltage range : 2.7V ~ 3.6V * Very low power consumption : Vcc = 3.0V C-grade: 23mA (@55ns) operating current I -grade: 25mA (@55ns) operating current C-grade: 15mA (@70ns) operating current I -grade: 16mA (@70ns) operating current 0.3uA(Typ.) CMOS standby current * High speed access time : -55 55ns -70 70ns * Automatic power down when chip is deselected * Three state outputs and TTL compatible * Fully static operation * Data retention supply voltage as low as 1.5V
* I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV2019 is a high performance , very low power CMOS Static Random Access Memory organized as 131,072 words by 16 bits and operates from a range of 2.7V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.3uA at 3.0V /25oC and maximum access time of 55ns at 2.7V / 85oC. Easy memory expansion is provided by active LOW chip enable (CE), active LOW output enable(OE) and three-state output drivers. The BS616LV2019 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV2019 is available in DICE form , JEDEC standard 48-pin TSOP Type I package and 48-ball BGA package.
PRODUCT FAMILY
PRODUCT FAMILY BS616LV2019DC BS616LV2019TC BS616LV2019AC BS616LV2019DI BS616LV2019TI BS616LV2019AI OPERATING TEMPERATURE Vcc RANGE SPEED
( ns )
55ns: 2.7~3.6V 70ns: 2.7~3.6V ( ICCSB1, Max ) Vcc=3.0V
POWER DISSIPATION STANDBY Operating
( ICC, Max ) Vcc=3.0V 55ns 70ns
PKG TYPE DICE TSOP1-48 BGA-48-0608 DICE TSOP1-48 BGA-48-0608
+0 O C to +70 O C
2.7V ~3.6V
55/70
3.0uA
23mA
15mA
-40 O C to +85 O C
2.7V ~ 3.6V
55/70
5.0uA
25mA
16mA
PIN CONFIGURATIONS
A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE CE2 NC /UB /LB NC NC A7 A6 A5 A4 A3 A2 A1 1 48 47 46 A16 NC VSS IO15 IO7 IO14 IO6 IO13 IO5 IO12 IO4 VCC IO11 IO3 IO10 IO2 IO9 IO1 IO8 IO0 /OE VSS /CE A0
BLOCK DIAGRAM
A8 A13 A15 A16 A14 A12 A7 A6 A5 A4 Address Input Buffer 20 Row Decoder 1024 Memory Array 1024 x 2048
9 10 13 16 17
BS616LV2019TC BS616LV2019TI
37
2048 DQ0 16 Data Input Buffer 16 Column I/O
27 24 1 A B C D E F G H LB D8 D9 VSS VCC D14 D15 N.C. 2 OE UB D10 D11 D12 D13 N.C. A8 3 A0 A3 A5 N.C. N.C. A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE D1 D3 D4 D5 WE A11 6 N.C. D0 D2 VCC VSS D6 D7 N.C. 25
. . . .
DQ15
. . . .
Write Driver
Sense Amp 128 Column Decoder
16
Data Output
16
Buffer
CE2 ,CE WE OE UB LB Vcc Gnd Control
14 Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2019
1
Revision 1.2 May 2004
BSI
PIN DESCRIPTIONS
BS616LV2019
Name
A0-A16 Address Input CE Chip Enable 1 Input CE2 Chip Enable 2 Input
Function
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM. CE is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. (48B BGA ignore CE2 pin) The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location.
WE Write Enable Input
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input DQ0 - DQ15 Data Input/Output Ports Vcc Gnd
Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
TRUTH TABLE
MODE Not selected (Power Down) Output Disabled Read CE H X X L L CE2 (1) X L X H H WE X X X H H OE X X X H L LB X X H X L H L L Write L H L X H L 1. 48B BGA ignore CE2 condition. UB X X H X L L H L L H D0~D7 High Z High Z High Z High Z Dout High Z Dout Din X Din D8~D15 High Z High Z High Z High Z Dout Dout High Z Din Din X Vcc CURRENT ICCSB , ICCSB1 ICCSB , ICCSB1 ICCSB , ICCSB1 ICC ICC ICC ICC ICC ICC ICC
R0201-BS616LV2019
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Revision 1.2 May 2004
BSI
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL V TERM V cc T BIAS T STG PT I OUT PARAMETER
Terminal Voltage with Respect to GND Power Supply Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
BS616LV2019
OPERATING RANGE
UNITS
V V
O
RATING
-0.5 to Vcc+0.5 -0.5 to Vcc+0.5 -40 to +85 -60 to +150 1.0 20
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0 C to +70 C -40 C to +85 C
O O O O
Vcc
2.7V ~ 3.6V 2.7V ~ 3.6V
C C
O
W mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CIN CDQ
PARAMETER Input Capacitance Input/Output Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V VI/O=0V
6 8
pF pF
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
PARAMETER NAME
VIL VIH IIL ILO VOL VOH ICC
(6)
PARAMETER
Guaranteed Input Low (2) Voltage Guaranteed Input High (2) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL
TEST CONDITIONS
Vcc =3.0V Vcc =3.0V Vcc = Max, VIN = 0V to Vcc Vcc = Max,CE = VIH or CE2 VI/O = 0V to Vcc Vcc = Max, IOL = 2.0mA Vcc = Min, IOH = -1.0mA CE = VIL, CE2 = VIH IDQ = 0mA, F = Fmax(3) CE=VIH or CE2 =VIL IDQ = 0mA
CEVcc-0.2V or CE2(4)0.2V, VINVcc-0.2V or VIN0.2V
(4) (4) (4)
MIN.
-0.3 2.0 --
TYP. (1) MAX.
-------0.8 Vcc+0.3 1 1 0.4 -16 25 0.5
UNITS V V uA uA V V mA
= VIL or OE = VIH, Vcc =3.0V Vcc =3.0V 3.0 V 70ns 55ns
--2.4 --
ICCSB ICCSB1(5)
Vcc =3.0V
--
--
mA
Standby Current-CMOS
Vcc =3.0V
--
0.3
5.0
uA
1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. 48B BGA ignore CE2 condition. 5.IccsB1_Max. is 3.0uA at Vcc=3.0V and TA=70oC. 3. Fmax = 1/tRC. 6. Icc_Max. is 23mA(@55ns) / 15mA(@70ns) at Vcc=3.0V/ 0~70oC.
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
SYMBOL
VDR ICCDR tCDR tR
(4)
PARAMETER
Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
O
TEST CONDITIONS
CE Vcc - 0.2V or CE2 0.2V , VIN Vcc - 0.2V or VIN 0.2V CE Vcc - 0.2V or CE2 0.2V(3), VIN Vcc - 0.2V or VIN 0.2V See Retention Waveform
(3)
MIN.
1.5 -0 TRC
(2)
TYP. (1)
-0.1 ---
MAX.
-1.0 ---
UNITS
V uA ns ns
1. Vcc = 1.5V, TA = + 25 C 3. 48B BGA ignore CE2 condition. R0201-BS616LV2019
2. tRC = Read Cycle Time 4. IccDR is 0.7uA at TA=70oC.
3
Revision 1.2 May 2004
BSI
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
BS616LV2019
VDR 1.5V
Vcc
VIH
Vcc
Vcc
t CDR
CE Vcc - 0.2V
tR
VIH
CE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
Vcc / 0V 1V/ns 0.5Vcc
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF "STATE
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load
CL = 100pF+1TTL CL = 30pF+1TTL
,
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE (48B BGA ignore CE2 condition)
JEDEC PARAMETER NAME PARAMETER NAME
CYCLE TIME : 55ns
DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Data Byte Control to Output High Z Output Disable to Output in High Z Data Hold from Address Change
CYCLE TIME : 70ns
(Vcc = 2.7~3.6V)
(Vcc = 2.7~3.6V)
MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
MIN. TYP. MAX.
tAVAX tAVQV tELQV tBA tGLQV t E1LQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX
tRC tAA tACS1 , 2 tBA (1) tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH
55 -(CE,CE2) (LB,UB) (CE,CE2) (LB,UB) (CE,CE2) (LB,UB) ---10 10 5 ---10
-------------
-55 55 30 30 ---30 30 25 --
70 ----10 10 5 ---10
-------------
-70 70 35 35 ---35 35 30 --
NOTE : 1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
R0201-BS616LV2019
4
Revision 1.2 May 2004
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS616LV2019
t RC
ADDRESS
t
D OUT
t
OH
AA
t OH
READ CYCLE2 (1,3,4)
CE2
tACS2(6) t
ACS1
CE
t
D OUT
(5,6) CLZ
t CHZ(5,6)
READ CYCLE3 (1,4)
ADDRESS
t RC
t
OE
AA
t
CE2
OE
t
OH
t t t t
(5,6) CLZ
ACS2(6)
CE
OLZ
ACS1
t t
OHZ CHZ
(5)
(1,5,6)
LB,UB
t
BE
t t
BA
BDO
D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. 6. 48B BGA ignore this parameters related to CE2 . R0201-BS616LV2019
5
Revision 1.2 May 2004
BSI
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) WRITE CYCLE (48B BGA ignore CE2 condition)
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION
Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time Date Byte Control to End of Write Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active
(Vcc = 2.7~3.6V)
BS616LV2019
CYCLE TIME : 55ns MIN. TYP. MAX. CYCLE TIME : 70ns
(Vcc = 2.7~3.6V)
MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ tWHOX
t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ t OW
55 (CE,CE2) 55 0 55 30 (CE,CE2,WE) (LB,UB) 0 25 -25 0 -5
-------------
-------25 --25 --
70 70 0 70 35 0 30 -30 0 -5
-------------
-------30 --30 --
NOTE : 1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
ADDRESS
t
WC
t WR
OE
(3)
CE2
(5,12)
t CW
CE
(5)
(11)
t
LB,UB
(5)
BW
t AW
WE
(3)
t AS
(4,10)
t WP
(2)
t OHZ
D OUT
t DH t DW
D IN R0201-BS616LV2019 Revision 1.2 May 2004
6
BSI
WRITE CYCLE2 (1,6)
BS616LV2019
t WC
ADDRESS
CE2
(5,12)
(11)
CE
(5)
t t
CW
BW
LB,UB
(5)
t
WE
AW
t WP
t WR
(3)
(2)
t AS
(4,10)
t WHZ
D OUT
t t DW t
OW
(7)
(8)
DH
(8,9)
D IN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE going low to the end of write. 12. 48B BGA ignore this parameters related to CE2 .
R0201-BS616LV2019
7
Revision 1.2 May 2004
BSI
ORDERING INFORMATION
BS616LV2019
BS616LV2019 X X
Z
YY
SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE T: TSOP1-48 A: BGA-48-0608 D: DICE
Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
PACKAGE DIMENSIONS
NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75
D1
e
VIEW A
48 mini-BGA (6 x 8)
R0201-BS616LV2019
E1
8
Revision 1.2 May 2004
BSI
PACKAGE DIMENSIONS
12(2X) 12(2X) HD UNIT SYMBOL 1 48 b E e
BS616LV2019
INCH 0.04330.004 A A1 0.0040.002 A2 0.0390.002 b 0.0090.002 b1 0.0080.001 c 0.004 ~ 0.008 c1 0.004 ~ 0.006 D 0.6450.004 E 0.4720.004 0.0200.004 e HD 0.7080.008 L 0.02360.006 L1 0.03150.004 y 0.004 Max. 0~ 8 MM 1.100.10 0.100.05 1.000.05 0.220.05 0.200.03 0.10 ~ 0.21 0.10 ~ 0.16 16.400.10 11.800.10 0.500.10 18.000.20 0.600.15 0.800.10 0.1 Max. 0~ 8
24
25 "A" D
Seating Plane
y
12(2x)
A
A2
GAUGE PLANE A 0.254
A1
24
25
SEATING PLANE 12(2x) WITH PLATING
A L L1
b
"A" DETAIL VIEW
c c1
BASE METAL
b1
SECTION A-A
1
48
TSOP1-48PIN
0
R0201-BS616LV2019
9
Revision 1.2 May 2004
BSI
REVISION HISTORY
Revision Description
1.1 1.2 Initial release Change Vcc_min from 2.4V to 2.7V
BS616LV2019
Date
Jan., 05, 2004 May, 03, 2004
Note
R0201-BS616LV2019
10
Revision 1.2 May 2004

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